? 1999 fairchild semiconductor corporation ds009961 www.fairchildsemi.com november 1988 revised november 1999 74ac377 ? 74act377 octal d-type flip-flop with clock enable 74ac377 74act377 octal d-type flip-flop with clock enable general description the ac/act377 has eight edge-triggered, d-type flip-flops with individual d inputs and q outputs. the common buff- ered clock (cp) input loads all flip-flops simultaneously, when the clock enable (ce ) is low. the register is fully edge-triggered. the state of each d input, one setup time before the low-to-high clock transi- tion, is transferred to the corresponding flip-flop?s q output. the ce input must be stable only one setup time prior to the low-to-high clock transition for predictable operation. features i cc reduced by 50% ideal for addressable register applications clock enable for address and data synchronization applications eight edge-triggered d-type flip-flops buffered common clock outputs source/sink 24 ma see 273 for master reset version see 373 for transparent latch version see 374 for 3-state version act377 has ttl-compatible inputs ordering code: device also available in tape and reel. specify by appending suffix letter ? x ? to the ordering code. connection diagram pin descriptions fact ? is a trademark of fairchild semiconductor corporation. order number package number package description 74ac377sc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300 ? wide body 74ac377sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74AC377MTC mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74ac377pc n20a 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300 ? wide 74act377sc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300 ? wide body 74act377sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74act377mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74act377pc n20a 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300 ? wide pin names description d 0 ? d 7 data inputs ce clock enable (active low) q 0 ? q 7 data outputs cp clock pulse input
www.fairchildsemi.com 2 74ac377 74act377 logic symbols ieee/iec mode select-function table h = high voltage level l = low voltage level x = immaterial = low-to-high clock transition logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays. operating mode inputs outputs cp ce d n q n load ? 1' lh h load ? 0' ll l hold (do nothing) h x no change x h x no change
3 www.fairchildsemi.com 74ac377 74act377 absolute maximum ratings (note 1) recommended operating conditions note 1: absolute maximum ratings are those values beyond which damage to the device may occur. the databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. fairchild does not recommend operation of fact ? circuits outside databook specifications. dc electrical characteristics for ac note 2: all outputs loaded; thresholds on input associated with output under test. note 3: maximum test duration 2.0 ms, one output loaded at a time. note 4: i in and i cc @ 3.0v are guaranteed to be less than or equal to the respective limit @ 5.5v v cc . supply voltage (v cc ) ? 0.5v to + 7.0v dc input diode current (i ik ) v i = ? 0.5v ? 20 ma v i = v cc + 0.5v + 20 ma dc input voltage (v i ) ? 0.5v to v cc + 0.5v dc output diode current (i ok ) v o = ? 0.5v ? 20 ma v o = v cc + 0.5v + 20 ma dc output voltage (v o ) ? 0.5v to v cc + 0.5v dc output source or sink current (i o ) 50 ma dc v cc or ground current per output pin (i cc or i gnd ) 50 ma storage temperature (t stg ) ? 65 c to + 150 c junction temperature (t j ) pdip 140 c supply voltage (v cc ) ac 2.0v to 6.0v act 4.5v to 5.5v input voltage (v i )0v to v cc output voltage (v o )0v to v cc operating temperature (t a ) ? 40 c to + 85 c minimum input edge rate ( ? v/ ? t) ac devices v in from 30% to 70% of v cc v cc @ 3.3v, 4.5v, 5.5v 125 mv/ns minimum input edge rate ( ? v/ ? t) act devices v in from 0.8v to 2.0v v cc @ 4.5v, 5.5v 125 mv/ns symbol parameter v cc t a = + 25 ct a = ? 40 c to + 85 c units conditions (v) typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1v input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 output voltage 4.5 4.49 4.4 4.4 v i out = ? 50 a 5.5 5.49 5.4 5.4 v in = v il or v ih 3.0 2.56 2.46 i oh = ? 12 ma 4.5 3.86 3.76 v i oh = ? 24 ma 5.5 4.86 4.76 i oh = ? 24 ma (note 2) v ol maximum low level 3.0 0.002 0.1 0.1 output voltage 4.5 0.001 0.1 0.1 v i out = 50 a 5.5 0.001 0.1 0.1 v in = v il or v ih 3.0 0.36 0.44 i ol = 12 ma 4.5 0.36 0.44 v i ol = 24 ma 5.5 0.36 0.44 i ol = 24 ma (note 2) i in maximum input 5.5 0.1 1.0 a v i = v cc , (note 4) leakage current gnd i old minimum dynamic 5.5 75 ma v old = 1.65v max i ohd output current (note 3) 5.5 ? 75 ma v ohd = 3.85v min i cc maximum quiescent 5.5 4.0 40.0 av in = v cc or gnd (note 4) supply current
www.fairchildsemi.com 4 74ac377 74act377 dc electrical characteristics for act note 5: all outputs loaded; thresholds on input associated with output under test. note 6: maximum test duration 2.0 ms, one output loaded at a time. ac electrical characteristics for ac note 7: voltage range 3.3 is 3.3v 0.3v voltage range 5.0 is 5.0v 0.5v symbol parameter v cc t a = + 25 ct a = ? 40 c to + 85 c units conditions (v) typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1v input voltage 5.5 1.5 2.0 2.0 or v cc ? 0.1v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1v input voltage 5.5 1.5 0.8 0.8 or v cc ? 0.1v v oh minimum high level 4.5 4.49 4.4 4.4 vi out = ? 50 a output voltage 5.5 5.49 5.4 5.4 v in = v il or v ih 4.5 3.86 3.76 v i oh = ? 24 ma 5.5 4.86 4.76 i oh = ? 24 ma (note 5) v ol maximum low level 4.5 0.001 0.1 0.1 vi out = 50 a output voltage 5.5 0.001 0.1 0.1 v in = v il or v ih 4.5 0.36 0.44 v i ol = 24 ma 5.5 0.36 0.44 i ol = 24 ma (note 5) i in maximum input 5.5 0.1 1.0 av i = v cc , gnd leakage current i cct maximum 5.5 0.6 1.5 ma v i = v cc ? 2.1v i cc /input i old minimum dynamic 5.5 75 ma v old = 1.65v max i ohd output current (note 6) 5.5 ? 75 ma v ohd = 3.85v min i cc maximum quiescent 5.5 4.0 40.0 a v in = v cc supply current or gnd v cc symbol parameter (v) t a = + 25 ct a = ? 40 c to + 85 c units (note 7) min typ max min max f max maximum clock 3.3 90 125 75 mhz frequency 5.0 140 175 125 t plh propagation delay 3.3 3.0 8.0 13.0 1.5 14.0 ns cp to q n 5.0 2.0 6.0 9.0 1.5 10.0 t phl propagation delay 3.3 3.5 8.5 13.0 2.0 14.5 ns cp to q n 5.0 2.5 6.5 10.0 1.5 11.0
5 www.fairchildsemi.com 74ac377 74act377 ac operating requirements for ac note 8: voltage range 3.3 is 3.0v 0.3v voltage range 5.0 is 5.0v 0.5v ac electrical characteristics for act note 9: voltage range 5.0 is 5.0v 0.5v ac operating requirements for act note 10: voltage range 5.0 is 5.0v 0.5v capacitance v cc t a = + 25 ct a = ? 40 c to + 85 c symbol parameter (v) c l = 50 pf c l = 50 pf units (note 8) typ guaranteed minimum t s setup time, high or low 3.3 3.5 5.5 6.0 ns d n to cp 5.0 2.5 4.0 4.5 t h hold time, high or low 3.3 ? 2.0 0 0 ns d n to cp 5.0 ? 1.0 1.0 1.0 t s setup time, high or low 3.3 4.0 6.0 7.5 ns ce to cp 5.0 2.5 4.0 4.5 t h hold time, high or low 3.3 ? 3.5 0 0 ns ce to cp 5.0 ? 2.0 1.0 1.0 t w cp pulse width 3.3 3.5 5.5 6.0 ns high or low 5.0 2.5 4.0 4.5 v cc t a = + 25 ct a = ? 40 c to + 85 c symbol parameter (v) c l = 50 pf c l = 50 pf units (note 9) min typ max min max f max maximum clock 5.0 140 175 125 mhz frequency t plh propagation delay 5.0 3.0 6.5 9.0 2.5 10.0 ns cp to q n t phl propagation delay 5.0 3.5 7.0 10.0 2.5 11.0 ns cp to q n v cc t a = + 25 ct a = ? 40 c to + 85 c symbol parameter (v) c l = 50 pf c l = 50 pf units (note 10) typ guaranteed minimum t s setup time, high or low 5.0 2.5 4.5 5.5 ns d n to cp t h hold time, high or low 5.0 ? 1.0 1.0 1.0 ns d n to cp t s setup time, high or low 5.0 2.5 4.5 5.5 ns ce to cp t h hold time, high or low 5.0 ? 1.0 1.0 1.0 ns ce to cp t w cp pulse width 5.0 2.0 4.0 4.5 ns high or low symbol parameter typ units conditions c in input capacitance 4.5 pf v cc = open c pd power dissipation capacitance 90.0 pf v cc = 5.0v
www.fairchildsemi.com 6 74ac377 74act377 physical dimensions inches (millimeters) unless otherwise noted 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300 ? wide body package number m20b
7 www.fairchildsemi.com 74ac377 74act377 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m20d
www.fairchildsemi.com 8 74ac377 74act377 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc20
9 www.fairchildsemi.com 74ac377 74act377 octal d-type flip-flop with clock enable physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300 ? wide package number n20a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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